Most mobile wireless communication devices comprise a hybrid of digital and analog electronics. For example, baseband signal processing is typically performed in Digital Signal Processors (DSP), with analog front-end receivers (low-noise amplifiers, frequency-selective filters, and the like) and transmitters (modulators, power amplifiers, and the like). Such hybrid designs present challenges in matching fabrication technology (e.g., CMOS digital and bipolar analog transistors), power distribution, noise mitigation, testing, and the like. Additionally, the decreasing supply voltage used to drive low power, high-speed digital baseband circuits imposes limits on analog RF component performance, particularly dynamic range. Accordingly, all-digital implementations for wireless communication circuits are of interest.
One known method of digital signal modulation is a delta-sigma (ΔΣ) modulator. The quantization noise of a ΔΣ modulator may be shifted to (higher) frequencies, and hence easily removed, by noise shaping. A representative first order Multi-stAge noise SHaping (MASH) ΔΣ modulator is depicted in FIG. 1. An M-bit MASH input signal is captured at a storage function, e.g., a latch or register. The latched input is added to the lower M−1 bits of the output, and the sum is latched. The signal of interest is the most significant bit (MSB), also commonly referred to as a Carry Out bit. The MASH ΔΣ modulator typically oversamples the input, often considerably so.
Better noise shaping may be obtained by serially concatenating a number of first order MASH ΔΣ modulators. FIG. 2 depicts a third order MASH ΔΣ modulator. The Carry Out signals from each modulator stage are combined using simple logic (e.g., buffers, inverters, registers) to generate a MASH output. For example, three Carry Out bits may be decoded to generate a 7-bit value for digital-to-analog conversion. At each successive stage of a MASH ΔΣ modulator, the quantization noise becomes more random, or whiter, and is hence more easily removed. See, e.g., R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, IEEE Press, 2005.
Oversampling MASH ΔΣ modulators must run at very high frequencies to implement practical RF transmitters. For example, a third order MASH ΔΣ modulator running at 5.4 GHz was constructed in 65 nm CMOS as part of a fully digital transmitter for a 2.4 to 2.7 GHz WiFi/WiMAX transceiver. See A. Pozsgay, et al., “A Fully Digital 65 nm CMOS Transmitter for the 2.4 to 2.7 GHz WiFi/WiMax Bands Using 5.4 GHz ΔΣ DACs,” International Solid State Circuits Conference (ISSCC), 2008, incorporated by reference herein in its entirety. At 5.4 GHz, the cycle time is less than 0.2 nsec. After allowance for clock-to-Q delay, setup time, and margin for clock skew, very little time remains between cycles to perform arithmetic or logical functions. This requires deeper pipelines, since the logic between registers is limited by propagation delay.